The distribution of digital video, audio, and other forms of complex information presents many design challenges. These challenges arise from the large storage requirements of such information, as well as the high bandwidth and processing requirements to distribute such information.
A high-performance information distribution system may include multiple processors, mass storage components, memories, and input/output components arranged to operate in a parallel (substantially simultaneous) fashion. Such systems, when properly designed, may provide for the simultaneous distribution of multiple high-resolution digital audio/video streams for cable television, the Internet, satellite television, and so on.
One performance limitation in such systems arises from mass storage. Mass storage generally involves large-capacity machine memory devices, such as magnetic and optical disks. Mass storage usually provides for the preservation of information (persistence) even in the absence of power applied to the memory. Mass storage generally provides a lower cost per storage metric than is available with smaller memories that lack persistence. For example, magnetic and optical disks generally provide a lower cost per megabyte, gigabyte, and terabyte of stored information than is available with non-persistent random access memory (RAM), flash memory, dynamic RAM (DRAM), static RAM (SRAM), and so on. However, mass storage is also generally characterized by slower read/write (access) times than smaller, non-persistent memories.
Cache memory may be provided to partially compensate for the slower read/write times of mass storage. Information of the mass storage that is frequently accessed may be duplicated in a cache memory that is, relative to the mass storage, lower in storage capacity and characterized by lower access times. Cache memories are typically non-persistent.
Various caching schemes are described by U.S. patents and/or published patent applications having numbers
a. U.S. Pat. No. 5,835,942
b. U.S. Pat. No. 6,463,509
c. U.S. Pat. No. 6,370,614
d. U.S. Pat. No. 6,370,615
e. U.S. Pat. No. 5,289,581
f. 20030005457
These patents describe schemes whereby cache memory benefits a particular processing node with which it is associated.
Various caching schemes are also described by U.S. patents and/or published patent applications having numbers
a. 20030095783
b. U.S. Pat. No. 6,061,504
c. U.S. Pat. No. 4,371,929
d. U.S. Pat. No. 4,977,495
e. U.S. Pat. No. 4,476,526
f. U.S. Pat. No. 4,394,733
These patents describe schemes whereby cache memory is globally available to processing nodes of the system.
U.S. patents and published patent applications having numbers
a. 20030200388
b. 20030177305
c. U.S. Pat. No. 6,467,022
d. describe “solid-state disk” memory schemes.
U.S. Pat. No. 4,920,478 describes a mass storage controller having an integrated cache memory.
U.S. Pat. No. 5,933,603 describes a buffering scheme.
U.S. Pat. No. 5,535,116 describes a global distributed memory scheme.
U.S. Pat. Nos. 5,893,163 and 5,860,101 describe a memory partitioning scheme including cache memory.
Global caching schemes tend to be expensive, complicated, and may tend to scale poorly as processing nodes are added to the system. Schemes that associate a cache with a particular processing node (including schemes that integrate a cache memory with a mass storage controller) may forfeit benefits available from underutilized caches on other nodes.